1. Field of the Invention:
The present invention relates to a non-volatile semiconductor programmable ROM with a bit error detector included therein.
2. Description of the Prior Art:
An EEPROM is a non-volatile memory capable of electrical erasing and writing of information therein, and has found in recent years extensive application. For example, an IC card includes therein an EEPROM IC in the form of a chip for use in storage of important data (deposit information and health information, etc.) by a user. The EEPROM is therefore required for a function of detecting any bit error involved in data in order to correctly store such informations. To detect any bit error caused in the EEPROM, it is well known to add a parity bit to bits constituting a word. For example, Nikkei Electronics (Sept. 26, 1983) describes a principle for detection and correction of bit errors in "A high speed 1M bit mask ROM including therein an ECC circuit for improvement of the yield". Means to detect any error in data and indicate its position will here be described with reference to the Nikkei Electronics article.
FIG. 2 is a prior art EEPROM system having an error detecting circuit which includes memory cells each storing of 1 word-that is-bits of data. The EEPROM system comprises data memory cells 10 for storing data D0 to D3, a data read circuit 30 for reading the data D0 to D3 stored in the data memory cells 10, bit lines 11 respectively, connecting the data memory cells 10 to parts of the read circuits 30, logical output lines 12 respectively connected to the read circuits 30 for outputting the data read by the read circuits 30, parity memory cells 20 for storing parity bits, parity bit lines 21 connected between the parity memory cells 20 and the remaining parts of the read circuits 30, a bit error detecting circuit 2 composed of exclusive OR gates EOR1 to EOR3 each connected to the read circuits 30 via the logical output lines 12, and a position indicating circuit 1 composed of AND gates AND1 to AND4 connected to the exclusive OR gates EOR1 to EOR3 via logical output lines 22 for outputting error bit-indicating outputs e0 to e3, the AND gates AND1 to AND4 including therein parity data Po to P2. The EEPROM system is adapted to provide the three parity memory cells 20 correspondingly to the four memory cells 10 for each word, and, further provide the parity memory cells 20 which respectively store pieces of parity information that respectively form even parities between the bit lines 21 and lines perpendicular thereto (word lines in general). Here, for example, the parity bit Po has an even parity relationship with the data D0, D2, and D3, the parity bit P1 and also has an even parity relationship with the data D2, D1, and D3, and the parity bit P2 further also has an even parity relationship with the data D0, D1, and D2. The bit error detecting circuit 2, i.e., the exclusive OR gate EOR1 to EOR3 respectively output a logical "0" signal when the even parity condition holds, and otherwise output a logical "1" signal. For example, the exclusive OR gate EOR2 has the input bit lines D0, D1, and D3. Assumed here that D0="0", D1="0", D2="1", D3="0", P0="1", P1="0", and P2="1", the EOR2 outputs a "0", satisfying the even parity condition. This assures no error. Provided now the data D1 is assumed to have an error bit "1" at a bit position where it should have a bit "0" originally, the EOR2 outputs a "1" as a result of its logic and the EOR3 also outputs a "1", causing the AND2 in the error position indicating circuit 1 to output a "1". This shows that the data D1 has a bit error therein. The prior art EEPROM system with the error detecting circuit shown in FIG. 2 required three parity bits when the number of data bits consituting 1 word was equal to four, as described above.
On such a principle, (N+1) parity memory cells is generally needed for 2.sup.N memory cells which constitute 1 word, to detect bit errors and to indicate bits in error. Additionally, the use of the even parity made it impossible to detect even bit errors. In other words, it was impossible to detect completely a plurality of errors involved in 1 word. From these reasons described above, the prior art EEPROM system with an error detecting circuit needed, upon fabrication thereof in a 1 word-8 bit construction, a 4 bit memory cell for each word, resulting in the total number of bits required to be increased by about 1.5 times in comparison to systems not including an error detecting circuit. The prior art EEPROM systems thus suffered from a problem in that the chip area was increased because of unsatifactory chip efficiency to cause an increase in the cost of the device. It further suffered from another problem in that there was an incomplete error detection for a plurality of bits.